1. Technical Field
The present invention relates generally to semiconductor fabrication, and more particularly, to a method for correcting a non-planar region by dynamically placing fill patterns separate from the product exposure.
2. Related Art
The ability to achieve and maintain surface planarity is becoming increasingly important for modern semiconductor processing. Processing is separated into two portions: front-end-of-line (FEOL), which includes operations performed on the semiconductor wafer in the course of device manufacturing up to first metallization, and back-end-of-line (BEOL). As semiconductor wafers enter the BEOL processing for copper damascene processing, a certain amount of non-planarity exists from the FEOL processing. Further non-planarity is normally produced by the BEOL processing and is inherent to copper damascene. For example, areas with high copper pattern factors polish at higher rates because less insulator area exists to distribute the force from the chemical mechanical polishing (CMP) pad than areas with low copper pattern factors. The production of non-planarity due to these differing polish rates is commonly referred to as “dishing.”
If high pattern factor regions are stacked on top of each other for several levels in a row, additive dishing effects can results in a region that is very low with respect to surrounding areas. It has been observed in such cases that long range peak to valley height differences across a chip can be approximately 3000 Å or more. Such severe height differences over a long range prevents sufficient planarization of, for example, anti-reflective coatings (ARC), underlayer resists or photoresist films. This situation has consequences for lithography since 3000 Å is on the order of the depth of focus for thin wire levels on, for example, 90 nm technologies.
Conventional lithography steppers generally scan the image in a slit which runs across the chip, continually reading the spatial position of the top of the resist along the slit with multiple optical sensors (the sensors basically detect the top of the resist). The instantaneous plane of best focus is decided by the stepper's software and the exposure plane is continually adjusted as the image is scanned. Since the image is focused in a plane but the wafer is non-planar across the chip by 3000 Å or more, some areas will be in much better focus than others areas. Poor lithography can result in the areas where the resist was exposed with the most “out of focus” conditions. For example, the poor focus areas can be so bad that the resist is not completely developed away in areas where it should be developed away. In other cases, the focus is not as poor but poor enough to result in (at least) critical dimension differences for minimum dimension features.
A severely dished area caused by cumulative dishing of several levels can also result in a metal “puddle” at the next level, depending on the design at the next level. A “puddle” results where CMP is unable to remove all of the metal without severe overpolish due to the depression. Even if enough metal is cleared to prevent hard shorts, the lines in this region could be taller than nominal, contributing to the spread in resistance tolerance.
The peak to valley topography can vary from run to run because of processing variations. For example, if one lot receives a longer effective liner overpolish (e.g., because liner thickness was at the low end of the specification or because the liner polish rate was at the high end of the specification, etc.), then more dishing can result. Center-to-edge differences in planarity after CMP can be also be significant, resulting either from non-uniformities inherent to CMP or from non-uniformities originating in other sectors such as metal deposition or insulator deposition. These center-to-edge differences can vary from run to run, or even from wafer to wafer within a run. Linewidth variations from run to run can also affect the amount of dishing in a certain region of the chip. For example, consider that a minimum equal line/space array at a second copper metallization level with a pitch of 280 nm and a nominal metal line width of 140 nm may vary from a low of approximately 39% pattern factor to a high of approximately 61% pattern factor over the allowable range of final critical dimension (e.g., approximately 110 to approximately 170 nm).
A number of approaches have been attempted to address the above-identified problems. In one approach, design restrictions are implemented on one level. Typically, this approach is implemented by imposing various design rules to narrow the range of allowable pattern factors. In another approach, design restrictions are applied to multiple levels. In this case, rules which prevent the placement of high pattern factors on top of one another may be imposed. Unfortunately, both of the above-described approaches can decrease design flexibility and circuit density.
In another approach, “holes” are placed in the metal in wide metal lines to reduce dishing. This approach is generally disadvantageous for high performance designs because it increases the resistance of lines, thus necessitating making lines even wider to account for the resistance increase. An analogous approach requires designers to break wide lines into narrower parallel lines, which is essentially another type of design restriction.
Another common technique places metal fill shapes on the product reticle between circuit wiring, where they can fit, to even out the pattern factor. The fill shapes are usually larger than the critical dimension and kept far enough away from circuit wiring so that there is no chance of shorting the fill shapes to circuit wiring. The metal fill helps to even out the pattern factor across the chip. The extent of the “evening out” achievable depends on the design, and also on the size of the pattern factor check box used. An improvement on this approach implements “smart” metal fill. In this case, instead of just placing fill in a standard fill pattern at a set pattern factor everywhere possible, an algorithm is used that examines the design environment and varies the metal fill on the product exposure to achieve better planarity results. One goal of the algorithm may be to even out the pattern factor as much as possible on a single level. Another goal of the algorithm might be to “compensate” for a high pattern factor area on one level by “lowering” the pattern factor directly above it at the next level, i.e., by essentially not placing metal fill there or placing a lower density metal fill there. The algorithm may also modulate the density of the metal fill by making the fill shapes larger or smaller, moving them further apart or closer together, etc. This approach, however, as well as all of the above-described approaches, cannot be used to make any adjustments to account for varying amounts of topography from lot-to-lot, from wafer-to-wafer within a lot or from edge-to-center (chip-to-chip) on a single wafer because once the metal fill pattern is selected, it is set for the particular product exposure and cannot be changed.
Finally, in another approach, planarization by CMP after interlayer dielectric (ILD) deposition can help to some extent, but this method cannot planarize well over very long distances. This approach also adds significant cost, and can cause additional defects.
In view of the foregoing, there is a need in the art for a way to use metal fill to improve planarization that does not suffer from the problems of the related art.